Area 2 Abstract

Area 2: Crystalline silicon materials and solar cells

SERIS, Singapore

Griddler 2.5 PRO: Modelling high efficiency solar cells with parameter database to calculate room for efficiency improvement

In research, pilot line or production line ramping, it is important to have a working model of each solar cell type so that the areas of efficiency improvement can be identified, in order to speed up the cell optimization process.  Griddler 2.5 PRO is a powerful solar cell finite element solver that models a solar cell down to the details of metallization grid pattern, print quality, edge isolation and passivation quality, front metal grid induced recombination, rear local contacts recombination and resistance, and rear silver pad recombination.  It also comes with a parameter database that allows the user to calculate the room for efficiency improvement with suitable process optimization or new technology adaptation.  In this talk, two examples of p-type localized BSF (LBSF) and n-type bifacial solar cell models will be presented, and various scenarios of efficiency improvement will be explored.

Sungkyunkwan University South Korea

Beyond 22% efficient silicon heterojunction solar cells with industrially feasible n-type front emitter

Silicon heterojunction (SHJ) solar cells are one of the potential candidates for the realization of low-cost high efficiency solar cells. Heterojunction solar cells were produced on n-type wafers with emitter located at the front side. The front emitter with a thick p-layer is choosen to have a high built in potential and conductivity. To reduce the front emitter thickness and improve the conductivity, the p-layer emitter can be replaced with n-layer emitter. The advantage of the n-layer front emitter is carrier transport improvement and increase in optical response at the front without any compromise in the open circuit voltage. Moreover the asymmetry in interface defect capture cross section is reduced with thin n-type front emitter and hence minority carrier lifetime increases. The reduction in wafer thickness reduces the recombination at the interface and hence the interface defect density is decreased.