24 - 28 October 2016 • Marina Bay Sands Sands Expo and Convention Centre, Singapore
Potential-induced degradation of the shunting type (PID-s) of silicon solar cells is attributed to planar crystal defects at the cell front surface. These so-called stacking faults with a length of a few micrometers, penetrating the p-n junction, behave as shunts when they are decorated with Na atoms. While the fundamental nature of PID-shunts is clear so far, the process of stacking fault formation is subject to ongoing investigations.
Recent work reveals that stacking faults grow in length and depth under sustained high voltage stress. This is a strong hint that the stacking faults evolve first upon application of the high voltage stress to the cell. A corresponding microscopic model of PID-shunt generation will be discussed in context to PID-s mitigation approaches as well as implications towards PID-s recovery modes.
Dr. Volker Naumann obtained his degree in physics in 2009 on Electric properties and microstructure of local contacts on silicon solar cells. Since 2010 he is with Fraunhofer Center for Silicon Photovoltaics CSP, Halle (Germany), working on electrical and surface analytical characterization of photovoltaic materials. In 2014 he finished his PhD at Martin-Luther-University Halle-Wittenberg with the thesis Root cause analysis and physical modelling for potential-induced degradation of silicon solar cells. His work area comprises electrical characterization, microstructural diagnostics and elemental analyses at silicon and thin films for photovoltaic applications. A particular focus of his work is on assessment and physical understanding of potential-induced degradation of silicon solar cells. He is author of more than 40 publications in journals and at conferences.